1. Field of the Invention
The present invention relates to a multilayer capacitor having through holes, more particularly relates to an easy-to-produce multilayer capacitor able to reduce the connection resistances between internal electrode layers in the stacking direction through the through holes while maintaining a low ESL without causing a reduction of the areas of the internal electrode layers.
2. Description of the Related Art
In recent years, the central processing units (CPUs) used for data processing systems have been made higher in operating frequency and have remarkably increased in consumed current due to improvements in their processing speed and their higher integration. Further, along with this, operating voltages have been reduced as a general tendency along with the reduction of the consumed power. Therefore, in the power supplies for supplying power to the CPUs, faster and larger current fluctuations are occurring. Keeping the voltage fluctuations accompanying such current fluctuations within the tolerances of the power supplies is becoming extremely difficult.
For this reason, multilayer capacitors functioning as smoothening capacitors are being arranged near CPUs while connected to the power supplies and are being frequently used as means for stabilization of the power supply. That is, at the time of high speed, transitory fluctuations in current, the multilayer capacitors quickly discharge to supply the CPUs with current and thereby keep down voltage fluctuations of the power supplies.
However, the increasingly higher operating frequencies of CPUs have led to faster speed and larger current fluctuations. The equivalent serial inductances (ESL) inherently possessed by the multilayer capacitors functioning as the smoothening capacitors are becoming relatively larger. As a result, the overall inductances including the equivalent serial inductances are now having a great effect on the voltage fluctuations of power supplies.
Therefore, as the structure of a conventional multilayer capacitor for reducing the ESL, there is for example the one disclosed in Japanese Patent Publication (A) No. 2001-284170. That is, this first publication discloses a structure designed to reduce the ESL by providing a plurality of terminal electrodes on each of the four side faces of a multilayer capacitor formed into a rectangular parallelepiped shape.
Further, as shown in Japanese Patent Publication (A) No. 2001-148324, a multilayer capacitor has been developed of a structure with external electrodes of isolated island shapes provided on at least one of the top and bottom surfaces of the multilayer capacitor and with these external electrodes connected by columnar shaped through hole electrodes to the internal electrode layers.
However, with a multilayer capacitor like in the first publication with pluralities of terminal electrodes provided on the four side faces and of a form for connection near a CPU, the ESL could not be sufficiently reduced and there were limits to the reduction of the overall inductance.
On the other hand, with a multilayer capacitor like in the second publication with island shaped external electrodes, the overall inductance becomes smaller and along with this higher speeds of CPUs can be handled. However, in a multilayer capacitor like in the second publication, a larger number of elongated through holes has to be formed inside the multilayer capacitor corresponding to the number of the external electrodes. This reduces the electrode areas of the internal electrode layers and is liable to reduce the electrostatic capacity.
Further, with elongated through holes, the connection resistances between the internal electrode layers in the stacking direction through the through holes are liable to increase and therefore the equivalent serial resistance (ESR) is liable to increase. Further, since a large number of elongated through holes are formed inside the multilayer capacitor, production of the multilayer capacitor becomes difficult. This becomes a factor increasing the production costs.